PIC18F6585 Datasheet, PDF (281/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
REGISTER 23-2: CANSTAT: CAN STATUS REGISTER
R-1
R-0
R-0
R-0
R-0
R-0
R-0
U-0
Mode 0 _{OPMODE2(1) OPMODE1(1) OPMODE0(1)}
—
ICODE2 ICODE1 ICODE0
—
R-1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Mode 1, 2 _{OPMODE2(1) OPMODE1(1) OPMODE0(1) EICODE4 EICODE3 EICODE2 EICODE1 EICODE0}
bit 7
bit 0
bit 7-5
bit 4
bit 3-1
bit 0
OPMODE2:OPMODE0: Operation Mode Status bits⁽¹⁾
111 = Reserved
110 = Reserved
101 = Reserved
100 = Configuration mode
011 = Listen Only mode
010 = Loopback mode
001 = Disable/Sleep mode
000 = Normal mode
Mode 0:
Unimplemented: Read as ‘0’
ICODE2:ICODE0: Interrupt Code bits in Mode 0
When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This
code indicates the source of the interrupt. By copying ICODE2:ICODE0 to WIN2:WIN0, it is pos-
sible to select the correct buffer to map into the Access Bank area. See Example 23-2 for a code
example.
No interrupt
Error interrupt
TXB2 interrupt
TXB1 interrupt
TXB0 interrupt
RXB1 interrupt
RXB0 interrupt
Wake-up interrupt
ICODE2:ICODE0 Value
000
001
010
011
100
101
110
111
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2004 Microchip Technology Inc.
DS30491C-page 279