PIC18F6585 Datasheet, PDF (74/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TXB1D7
TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72 TXB1D71 TXB1D70 xxxx xxxx 42, 230
TXB1D6
TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62 TXB1D61 TXB1D60 xxxx xxxx 42, 230
TXB1D5
TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52 TXB1D51 TXB1D50 xxxx xxxx 42, 230
TXB1D4
TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42 TXB1D41 TXB1D40 xxxx xxxx 42, 230
TXB1D3
TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32 TXB1D31 TXB1D30 xxxx xxxx 42, 230
TXB1D2
TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22 TXB1D21 TXB1D20 xxxx xxxx 42, 230
TXB1D1
TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12 TXB1D11 TXB1D10 xxxx xxxx 42, 230
TXB1D0
TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02 TXB1D01 TXB1D00 xxxx xxxx 42, 230
TXB1DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0 -x-- xxxx 42, 230
TXB1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 42, 230
TXB1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 42, 230
TXB1SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16 xx-x x-xx 42, 230
TXB1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 42, 230
TXB1CON
Mode 0
—
TXABT
TXLARB TXERR TXREQ
—
TXPRI1 TXPRI0 -000 0-00 42, 230
TXB1CON
Mode 1, 2
TXBIF
TXABT
TXLARB TXERR TXREQ
—
TXPRI1 TXPRI0 0000 0-00 42, 230
TXB2D7
TXB2D77 TXB2D76 TXB2D75 TXB2D74 TXB2D73 TXB2D72 TXB2D71 TXB2D70 xxxx xxxx 42, 230
TXB2D6
TXB2D67 TXB2D66 TXB2D65 TXB2D64 TXB2D63 TXB2D62 TXB2D61 TXB2D60 xxxx xxxx 42, 230
TXB2D5
TXB2D57 TXB2D56 TXB2D55 TXB2D54 TXB2D53 TXB2D52 TXB2D51 TXB2D50 xxxx xxxx 42, 230
TXB2D4
TXB2D47 TXB2D46 TXB2D45 TXB2D44 TXB2D43 TXB2D42 TXB2D41 TXB2D40 xxxx xxxx 42, 230
TXB2D3
TXB2D37 TXB2D36 TXB2D35 TXB2D34 TXB2D33 TXB2D32 TXB2D31 TXB2D30 xxxx xxxx 42, 230
TXB2D2
TXB2D27 TXB2D26 TXB2D25 TXB2D24 TXB2D23 TXB2D22 TXB2D21 TXB2D20 xxxx xxxx 42, 230
TXB2D1
TXB2D17 TXB2D16 TXB2D15 TXB2D14 TXB2D13 TXB2D12 TXB2D11 TXB2D10 xxxx xxxx 42, 230
TXB2D0
TXB2D07 TXB2D06 TXB2D05 TXB2D04 TXB2D03 TXB2D02 TXB2D01 TXB2D00 xxxx xxxx 42, 230
TXB2DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0 -x-- xxxx 42, 230
TXB2EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 42, 230
TXB2EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 42, 230
TXB2SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16 xxx- x-xx 42, 230
TXB2SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 42, 230
TXB2CON
Mode 0
—
TXABT
TXLARB TXERR TXREQ
—
TXPRI1 TXPRI0 -000 0-00 42, 230
TXB2CON
Mode 1, 2
TXBIF
TXABT
TXLARB TXERR TXREQ
—
TXPRI1 TXPRI0 0000 0-00 42, 230
RXM1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 42, 230
RXM1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 43, 230
RXM1SIDL
SID2
SID1
SID0
—
EXIDEN
—
EID17
EID16 xx-x 0-xx 43, 230
RXM1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3 xxxx xxxx 43, 230
RXM0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0 xxxx xxxx 43, 230
RXM0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8 xxxx xxxx 43, 230
RXM0SIDL
SID2
SID1
SID0
—
EXIDM
—
EID17
EID16 xx-x 0-xx 43, 230
RXM0SIDH
RXF15EIDL⁽⁷⁾
SID10
EID7
SID9
EID6
SID8
EID5
SID7
EID4
SID6
EID3
SID5
EID2
SID4
EID1
SID3
EID0
xxxx xxxx 43, 230
xxxx xxxx 47, 230
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator
modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X80 devices; always maintain these clear.
These bits have multiple functions depending on the CAN module mode selection.
Meaning of this register depends on whether this buffer is configured as transmit or receive.
RG5 is available as an input when MCLR is disabled.
This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.
DS30491C-page 72
 2004 Microchip Technology Inc.