PIC18F6585 Datasheet, PDF (105/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
7.3 Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>), clear the CFGS control bit
(EECON1<6>) and then set control bit, RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation or until it is written to
by the user (during a write operation).
EXAMPLE 7-1: DATA EEPROM READ
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
DATA_EE_ADR_HI
EEADRH
DATA_EE_ADDR_LOW
EEADR
EECON1, EEPGD
EECON1, CFGS
EECON1, RD
EEDATA, W
;
;
;
; Data Memory Address to read
; Point to DATA memory
; Access program Flash or Data EEPROM memory
; EEPROM Read
; W = EEDATA
7.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. Then the
sequence in Example 7-2 must be followed to initiate
the write cycle.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADRH:EEADR and EDATA cannot be modified. The
WR bit will be inhibited from being set unless the
WREN bit is set. The WREN bit must be set on a pre-
vious instruction. Both WR and WREN cannot be set
with the same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. The user may either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
EXAMPLE 7-2: DATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
DATA_EE_ADDR_HI
EEADRH
DATA_EE_ADDR_LOW
EEADR
DATA_EE_DATA
EEDATA
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
Required
Sequence
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
.
.
.
BCF
EECON1, WREN
;
;
;
; Data Memory Address to read
;
; Data Memory Value to write
; Point to DATA memory
; Access program Flash or Data EEPROM memory
; Enable writes
; Disable interrupts
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Enable interrupts
; user code execution
; Disable writes on write complete (EEIF set)
 2004 Microchip Technology Inc.
DS30491C-page 103