PIC18F6585 Datasheet, PDF (239/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
18.2 USART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
USART uses standard Non-Return-to-Zero (NRZ) for-
mat (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The USART transmits and receives the LSb first. The
USART’s transmitter and receiver are functionally inde-
pendent but use the same data format and baud rate.
The Baud Rate Generator produces a clock, either x16
or x64 of the bit shift rate depending on the BRGH and
BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity is
not supported by the hardware but can be implemented
in software and stored as the 9th data bit.
Asynchronous mode is available in all low-power
modes; it is available in Sleep mode only when auto-
wake-up on sync break is enabled. When in PRI_IDLE
mode, no changes to the Baud Rate Generator values
are required; however, other low-power mode clocks
may operate at another frequency than the primary
clock. Therefore, the Baud Rate Generator values may
need to be adjusted.
When operating in Asynchronous mode, the USART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
18.2.1 USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 18-2. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the Stop bit has been
transmitted from the previous load. As soon as the Stop
bit is transmitted, the TSR is loaded with new data from
the TXREG register (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is
empty and flag bit TXIF (PIR1<4>) is set. This interrupt
can be enabled/disabled by setting/clearing enable bit
TXIE (PIE1<4>). Flag bit TXIF will be set regardless of
the state of enable bit TXIE and cannot be cleared in
software. Flag bit TXIF is not cleared immediately upon
loading the Transmit Buffer register, TXREG. TXIF
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following
a load of TXREG will return invalid results.
While flag bit TXIF indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. Status bit TRMT is a read-
only bit which is set when the TSR register is empty. No
interrupt logic is tied to this bit, so the user has to poll
this bit in order to determine if the TSR register is
empty.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
To set up an Asynchronous Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Note: When BRGH and BRG16 bits are set,
SPBRGH:SPBRG must be more than ‘1’.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
 2004 Microchip Technology Inc.
DS30491C-page 237