|
PIC18F6585 Datasheet, PDF (361/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module | |||
|
◁ |
PIC18F6585/8585/6680/8680
24.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro® devices.
The user program memory is divided on binary bound-
aries into four blocks of 16 Kbytes each. The first block
is further divided into a boot block of 2048 bytes and a
second block (Block 0) of 14 Kbytes.
Each of the blocks has three code protection bits
associated with them. They are:
⢠Code-Protect bit (CPn)
⢠Write-Protect bit (WRTn)
⢠External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
FIGURE 24-3:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18FXX8X DEVICES
MEMORY SIZE/DEVICE
48 Kbytes
(PIC18FX585
64 Kbytes
(PIC18FX680)
Boot Block
Boot Block
Block 0
Block 0
Block 1
Block 1
Block 2
Block 2
Unimplemented Read â0â
Block 3
Address
Range
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
Block Code Protection
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
300008h CONFIG5L â
â
â
300009h CONFIG5H CPD
CPB
â
30000Ah CONFIG6L â
â
â
30000Bh CONFIG6H WRTD WRTB WRTC
30000Ch CONFIG7L â
â
â
30000Dh CONFIG7H â
EBTRB
â
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX585 devices.
â
CP3(1)
â
â
â
WRT3(1)
â
â
â
EBTR3(1)
â
â
Bit 2
CP2
â
WRT2
â
EBTR2
â
Bit 1
CP1
â
WRT1
â
EBTR1
â
Bit 0
CP0
â
WRT0
â
EBTR0
â
 2004 Microchip Technology Inc.
DS30491C-page 359
|
▷ |