PIC18F6585 Datasheet, PDF (31/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
If the main oscillator is configured for HS mode with
PLL active, an oscillator start-up time (TOST) plus an
additional PLL time-out (TPLL) will occur. The PLL time-
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for HS-PLL mode, is shown in Figure 2-10.
If the main oscillator is configured for EC mode with PLL
active, only the PLL time-out (TPLL) will occur. The PLL
time-out is typically 2 ms and allows the PLL to lock to
the main oscillator frequency. A timing diagram, indicat-
ing the transition from the Timer1 oscillator to the main
oscillator for EC with PLL active, is shown in Figure 2-11.
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(HS WITH PLL ACTIVE, SCS1 = 1)
Q4
Q1
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI
OSC1
PLL Clock
Input
TOST
TPLL
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC
TOSC
1
TSCS
23 4 56 78
PC + 2
PC + 4
Note:
TOST = 1024 TOSC (drawing not to scale).
FIGURE 2-11:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(EC WITH PLL ACTIVE, SCS1 = 1)
Q4
Q1
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI
OSC1
PLL Clock
Input
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC
TPLL
TOSC
1
TSCS
23 4 56 78
PC + 2
PC + 4
 2004 Microchip Technology Inc.
DS30491C-page 29