PIC18F6585 Datasheet, PDF (295/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
REGISTER 23-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER
R/C-0
Mode 0 _RXFUL
R/W-0
RXM1
R/W-0
RXM0
U-0
R-0
R/W-0
—
RXRTRRO
FILHIT2
R-0
FILHIT1
R-0
FILHIT0
R/C-0
Mode 1, 2
RXFUL
bit 7
R/W-0
RXM1
R-0
RTRRO
R-0
FILHIT4
R-0
FILHIT3
R-0
FILHIT2
R-0
FILHIT1
R-0
FILHIT0
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RXFUL: Receive Full Status bit
1 = Receive buffer contains a received message
0 = Receive buffer is open to receive a new message
Note:
This bit is set by the CAN module upon receiving a message and must be cleared by software after
the buffer is read. As long as RXFUL is set, no new message will be loaded and buffer will be
considered full.
Mode 0:
RXM1: Receive Buffer Mode bit 1; combines with RXM0 to form RXM<1:0> bits (see bit 5)
11 = Receive all messages (including those with errors); filter criteria is ignored
10 = Receive only valid messages with extended identifier; EXIDEN in RXFnSIDL must be ‘1’
01 = Receive only valid messages with standard identifier, EXIDEN in RXFnSIDL must be ‘0’
00 = Receive all valid messages as per EXIDEN bit in RXFnSIDL register
Mode 1, 2:
RXM1: Receive Buffer Mode bit
1 = Receive all messages (including those with errors); acceptance filters are ignored
0 = Receive all valid messages as per acceptance filters
Mode 0:
RXM0: Receive Buffer Mode bit 0; combines with RXM1 to form RXM<1:0> bits (see bit 6)
Mode 1, 2:
RTRRO: Remote Transmission Request bit for Received Message (read-only)
1 = A remote transmission request is received
0 = A remote transmission request is not received
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
FILHIT4: Filter Hit bit 4
This bit combines with other bits to form filter acceptance bits <4:0>.
Mode 0:
RXRTRRO: Remote Transmission Request bit for Received Message (read-only)
1 = A remote transmission request is received
0 = A remote transmission request is not received
Mode 1, 2:
FILHIT3: Filter Hit bit 3
This bit combines with other bits to form filter acceptance bits <4:0>.
Mode 0:
FILHIT2:FILHIT0: Filter Hit bits
These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1.
111 = Reserved
110 = Reserved
101 = Acceptance Filter 5 (RXF5)
100 = Acceptance Filter 4 (RXF4)
011 = Acceptance Filter 3 (RXF3)
010 = Acceptance Filter 2 (RXF2)
001 = Acceptance Filter 1 (RXF1), only possible when RXB0DBEN bit is set
000 = Acceptance Filter 0 (RXF0), only possible when RXB0DBEN bit is set
Mode 1, 2:
FILHIT2:FILHIT0 Filter Hit bits <2:0>
These bits, in combination with FILHIT<4:3>, indicate which acceptance filter enabled the message reception
into this receive buffer.
01111 = Acceptance Filter 15 (RXF15)
01110 = Acceptance Filter 14 (RXF14)
...
00000 = Acceptance Filter 0 (RXF0)
Legend:
C = Clearable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
 2004 Microchip Technology Inc.
DS30491C-page 293