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PIC18F6585 Datasheet, PDF (402/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module
PIC18F6585/8585/6680/8680
SLEEP
Enter Sleep mode
Syntax:
[ label ] SLEEP
Operands:
None
Operation:
00h → WDT,
0 → WDT postscaler,
1 → TO,
0 → PD
Status Affected: TO, PD
Encoding:
0000 0000 0000 0011
Description:
The Power-down status bit (PD) is
cleared. The Time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
No
operation
Q3
Process
Data
Q4
Go to
SLEEP
Example:
SLEEP
Before Instruction
TO = ?
PD = ?
After Instruction
TO = 1 †
PD = 0
† If WDT causes wake-up, this bit is cleared.
SUBFWP
Subtract f from W with borrow
Syntax:
[ label ] SUBFWB f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(W) – (f) – (C) → dest
Status Affected: N, OV, C, DC, Z
Encoding:
0101 01da ffff ffff
Description:
Subtract register ‘f’ and carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored in register ‘f’ (default). If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR
value. If ‘a’ is ‘1’, then the bank will
be selected as per the BSR value
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example 1:
SUBFWB REG, 1, 0
Before Instruction
REG
W
C
=3
=2
=1
After Instruction
REG
W
C
Z
N
= FF
=2
=0
=0
= 1 ; result is negative
Example 2:
SUBFWB REG, 0, 0
Before Instruction
REG
W
C
=2
=5
=1
After Instruction
REG
W
C
Z
N
=2
=3
=1
=0
=0
; result is positive
Example 3:
SUBFWB REG, 1, 0
Before Instruction
REG
W
C
=1
=2
=0
After Instruction
REG
W
C
Z
N
=0
=2
=1
=1
=0
; result is zero
DS30491C-page 400
 2004 Microchip Technology Inc.