PIC18F6585 Datasheet, PDF (22/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X8X
PIC18F8X8X
Pin
Type
TQFP PLCC TQFP
Buffer
Type
Description
PORTH is a bidirectional I/O port⁽⁵⁾.
RH0/A16
RH0
A16
—
—
79
I/O
ST
Digital I/O.
O
TTL
External memory address 16.
RH1/A17
RH1
A17
—
—
80
I/O
ST
Digital I/O.
O
TTL
External memory address 17.
RH2/A18
RH2
A18
—
—
1
I/O
ST
Digital I/O.
O
TTL
External memory address 18.
RH3/A19
RH3
A19
—
—
2
I/O
ST
Digital I/O.
O
TTL
External memory address 19.
RH4/AN12
RH4
AN12
—
—
22
I/O
ST
Digital I/O.
I Analog
Analog input 12.
RH5/AN13
RH5
AN13
—
—
21
I/O
ST
Digital I/O.
I Analog
Analog input 13.
RH6/AN14/P1C
RH6
AN14
P1C⁽⁷⁾
—
—
20
I/O
ST
Digital I/O.
I Analog
Analog input 14.
I/O
ST
Alternate CCP1 PWM output C.
RH7/AN15/P1B
RH7
AN15
P1B⁽⁷⁾
—
—
19
I/O
ST
Digital I/O.
I Analog
Analog input 15.
Alternate CCP1 PWM output B.
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I
= Input
P = Power
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.
Default assignment when CCP2MX is set.
External memory interface functions are only available on PIC18F8X8X devices.
CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is
multiplexed with either RB3 or RC1.
PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
PSP is available in Microcontroller mode only.
On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX
configuration bit.
DS30491C-page 20
 2004 Microchip Technology Inc.