PIC18F6585 Datasheet, PDF (39/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
PIC18F6X8X PIC18F8X8X
---- xxxx
---- uuuu
---- uuuu
FSR1L
PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
INDF2
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
---- 0000
N/A
---- 0000
N/A
---- uuuu
N/A
POSTINC2 PIC18F6X8X PIC18F8X8X
N/A
N/A
N/A
POSTDEC2 PIC18F6X8X PIC18F8X8X
N/A
N/A
N/A
PREINC2
PIC18F6X8X PIC18F8X8X
N/A
N/A
N/A
PLUSW2
PIC18F6X8X PIC18F8X8X
N/A
N/A
N/A
FSR2H
PIC18F6X8X PIC18F8X8X
---- xxxx
---- uuuu
---- uuuu
FSR2L
PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
PIC18F6X8X PIC18F8X8X
---x xxxx
---u uuuu
---u uuuu
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
0000 0000
xxxx xxxx
1111 1111
---- 0000
--00 0101
uuuu uuuu
uuuu uuuu
1111 1111
---- 0000
--00 0101
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
--uu uuuu
WDTCON
RCON⁽⁴⁾
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
---- ---0
0--q 11qq
---- ---0
0--q qquu
---- ---u
u--u qquu
TMR1H
PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
TMR2
PR2
T2CON
SSPBUF
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
PIC18F6X8X PIC18F8X8X
0-00 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
u-uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
SSPADD
PIC18F6X8X PIC18F8X8X
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
PIC18F6X8X PIC18F8X8X
0000 0000
0000 0000
uuuu uuuu
SSPCON1 PIC18F6X8X PIC18F8X8X
0000 0000
0000 0000
uuuu uuuu
SSPCON2 PIC18F6X8X PIC18F8X8X
0000 0000
0000 0000
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 3-2 for Reset value for specific condition.
Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.
This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.
 2004 Microchip Technology Inc.
DS30491C-page 37