PIC18F6585 Datasheet, PDF (485/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
TXBIE (Transmit Buffers
Interrupt Enable) ............................................... 322
TXBnCON (Transmit Buffer n
Control) ............................................................. 285
TXBnDLC (Transmit Buffer n
Data Length Code) ........................................... 288
TXBnDm (Transmit Buffer n
Data Field Byte m) ............................................ 287
TXBnEIDH (Transmit Buffer n
Extended Identifier, High Byte) ......................... 286
TXBnEIDL (Transmit Buffer n
Extended Identifier, Low Byte) .......................... 287
TXBnSIDH (Transmit Buffer n
Standard Identifier, High Byte).......................... 286
TXBnSIDL (Transmit Buffer n
Standard Identifier, Low Byte) .......................... 286
TXERRCNT (Transmit Error Count) ......................... 288
TXSTA (Transmit Status and
Control) ............................................................. 230
WDTCON (Watchdog Timer
Control) ............................................................. 355
RESET .............................................................................. 395
Reset........................................................................... 33, 345
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer and
Brown-out Reset Requirements................................ 433
RETFIE ............................................................................. 396
RETLW ............................................................................. 396
RETURN ........................................................................... 397
Return Address Stack
and Associated Registers ........................................... 55
Stack Pointer (STKPTR) ............................................. 54
Top-of-Stack Access................................................... 54
Revision History ................................................................ 469
RLCF................................................................................. 397
RLNCF .............................................................................. 398
RRCF ................................................................................ 398
RRNCF ............................................................................. 399
S
SCK................................................................................... 189
SDI .................................................................................... 189
SDO .................................................................................. 189
Serial Clock, SCK ............................................................. 189
Serial Data In, SDI ............................................................ 189
Serial Data Out, SDO........................................................ 189
Serial Peripheral Interface. See SPI.
SETF ................................................................................. 399
Slave Select, SS ............................................................... 189
SLEEP .............................................................................. 400
Sleep ......................................................................... 345, 357
Software Simulator
(MPLAB SIM) ............................................................ 408
Software Simulator
(MPLAB SIM30) ........................................................ 408
Special Event Trigger. See Compare.
Special Features of the CPU ............................................ 345
Configuration Registers .................................... 347–353
Special Function Registers ................................................. 59
Map ............................................................................. 61
SPI
Serial Clock .............................................................. 189
Serial Data In............................................................ 189
Serial Data Out ......................................................... 189
Slave Select.............................................................. 189
SPI Mode.................................................................. 189
SPI Master/Slave Connection........................................... 193
SPI Mode
Master/Slave Connection ......................................... 193
SS ..................................................................................... 189
SSP
TMR2 Output for Clock Shift............................. 162, 163
SSPOV Status Flag .......................................................... 219
SSPSTAT Register
R/W Bit ............................................................. 202, 203
Status Bits
Significance and Initialization
Condition for RCON Register ............................. 35
SUBFWP .......................................................................... 400
SUBLW ............................................................................. 401
SUBWF............................................................................. 401
SUBWFB .......................................................................... 402
SWAPF ............................................................................. 402
T
Table Pointer Operations
(table) ......................................................................... 86
TBLRD .............................................................................. 403
TBLWT ............................................................................. 404
Time-out in Various
Situations.................................................................... 35
Time-out Sequence ............................................................ 34
Timer0 .............................................................................. 155
16-bit Mode Timer Reads and
Writes ............................................................... 157
Associated Registers................................................ 157
Clock Source Edge Select
(T0SE Bit) ......................................................... 157
Clock Source Select
(T0CS Bit)......................................................... 157
Operation.................................................................. 157
Overflow Interrupt ..................................................... 157
Prescaler .................................................................. 157
Switching Assignment ...................................... 157
Prescaler. See Prescaler, Timer0.
Timer0 and Timer1 External Clock
Requirements ........................................................... 434
Timer1 .............................................................................. 159
16-bit Read/Write Mode............................................ 161
Associated Registers................................................ 161
Operation.................................................................. 160
Oscillator........................................................... 159, 161
Overflow Interrupt ............................................. 159, 161
Special Event Trigger
(CCP)........................................................ 161, 171
TMR1H Register....................................................... 159
TMR1L Register ....................................................... 159
 2004 Microchip Technology Inc.
DS30491C-page 483