PIC18F6585 Datasheet, PDF (294/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED)
bit 2
Mode 0:
RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit
1 = Receive Buffer 0 overflow will write to Receive Buffer 1
0 = No Receive Buffer 0 overflow to Receive Buffer 1
Mode 1, 2:
FILHIT2: Filter Hit bit 2
This bit combines with other bits to form filter acceptance bits <4:0>.
bit 1
Mode 0:
JTOFF: Jump Table Offset bit (read-only copy of RXB0DBEN)
1 = Allows jump table offset between 6 and 7
0 = Allows jump table offset between 1 and 0
Note: This bit allows same filter jump table for both RXB0CON and RXB1CON.
Mode 1, 2:
FILHIT1: Filter Hit bit 1
This bit combines with other bits to form filter acceptance bits <4:0>.
bit 0
Mode 0:
FILHIT0: Filter Hit bit 0
This bit indicates which acceptance filter enabled the message reception into Receive Buffer 0.
1 = Acceptance Filter 1 (RXF1)
0 = Acceptance Filter 0 (RXF0)
Mode 1, 2:
FILHIT0: Filter Hit bit 0
This bit, in combination with FILHIT<4:1>, indicates which acceptance filter enabled the
message reception into this receive buffer.
01111 = Acceptance Filter 15 (RXF15)
01110 = Acceptance Filter 14 (RXF14)
...
00000 = Acceptance Filter 0 (RXF0)
Legend:
C = Clearable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
DS30491C-page 292
 2004 Microchip Technology Inc.