PIC18F6585 Datasheet, PDF (178/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
16.1 ECCP Outputs
The enhanced CCP module may have up to four
outputs depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins RC2, RE6, RE5 and RG4.
The pin assignments are summarized in Table 16-1.
To configure I/O pins as PWM outputs, the proper PWM
mode must be selected by setting the P1Mx and
CCP1Mx bits (CCP1CON<7:6> and <3:0>, respec-
tively). The appropriate TRIS direction bits for the port
pins must also be set as outputs.
TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
ECCP Mode
CCP1CON
Configuration
RC2
RE6
RE5
RG4
Compatible CCP 00xx11xx
CCP1
RE6
RE5
RG4
Dual PWM
10xx11xx
P1A
P1B⁽²⁾
RE5
RG4
Quad PWM
x1xx11xx
P1A
P1B⁽²⁾
P1C⁽²⁾
P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1: TRIS register values must be configured appropriately.
2: On PIC18F8X8X devices, these pins can be alternately multiplexed with RH7 or RH6 by changing the
ECCPMX configuration bit.
FIGURE 16-1:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1 or Timer3, but will not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion.
Set Flag bit CCP1IF
RB3/CCP1/P1A pin
TRISB<3>
Output Enable
QS
R
Output
Logic
CCP1CON<3:0>
Mode Select
Match
CCPR1H CCPR1L
Comparator
T3CCP2
01
TMR1H TMR1L
TMR3H TMR3L
DS30491C-page 176
 2004 Microchip Technology Inc.