PIC18F6585 Datasheet, PDF (172/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
15.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCPxIE (PIE registers) clear to avoid false interrupts
and should clear the flag bit, CCPxIF, following any
such change in operating mode.
15.2.4 CCP PRESCALER
There are four prescaler settings specified by bits
CCPxM3:CCPxM0. Whenever the CCPx module is
turned off, or the CCPx module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. The prescaler counter will not be
cleared; therefore, the first capture may be from a
non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
15.2.5 CAN MESSAGE TIME-STAMP
The CAN capture event occurs when a message is
received in any of the receive buffers. When config-
ured, the CAN module provides the trigger to the CCP1
module to cause a capture event. This feature is
provided to time-stamp the received CAN messages.
This feature is enabled by setting the CANCAP bit of
the CAN I/O Control register (CIOCON<4>). The
message receive signal from the CAN module then
takes the place of the events on RC2/CCP1.
EXAMPLE 15-1: CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF CCP1CON
MOVLW NEW_CAPT_PS
MOVWF CCP1CON
; Turn CCP module off
; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
CCP1 pin
Prescaler
÷ 1, 4, 16
Set Flag bit CCP1IF
T3CCP2
and
Edge Detect
T3CCP2
CCP2 pin
CCP1CON<3:0>
Q’s
Set Flag bit CCP2IF
T3CCP1
T3CCP2
Prescaler
÷ 1, 4, 16
and
Edge Detect
CCP2CON<3:0>
Q’s
T3CCP2
T3CCP1
TMR3H TMR3L
TMR3
Enable
CCPR1H
CCPR1L
TMR1
Enable
TMR1H
TMR1L
TMR3H TMR3L
TMR3
Enable
CCPR2H CCPR2L
TMR1
Enable
TMR1H
TMR1L
DS30491C-page 170
 2004 Microchip Technology Inc.