PIC18F6585 Datasheet, PDF (53/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
4.0 MEMORY ORGANIZATION
There are three memory blocks in
PIC18F6585/8585/6680/8680 devices. They are:
• Program Memory
• Data RAM
• Data EEPROM
Data and program memory use separate busses which
allows for concurrent access of these blocks. Additional
detailed information for Flash program memory and data
EEPROM is provided in Section 5.0 “Flash Program
Memory” and Section 7.0 “Data EEPROM Memory”,
respectively.
In addition to on-chip Flash, the PIC18F8X8X devices
are also capable of accessing external program mem-
ory through an external memory bus. Depending on the
selected operating mode (discussed in Section 4.1.1
“PIC18F8X8X Program Memory Modes”), the
controllers may access either internal or external pro-
gram memory exclusively, or both internal and external
memory in selected blocks. Additional information on
the external memory interface is provided in
Section 6.0 “External Memory Interface”.
4.1 Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
The PIC18F6585 and PIC18F8585 each have
48 Kbytes of on-chip Flash memory, while the
PIC18F6680 and PIC18F8680 have 64 Kbytes of Flash.
This means that PIC18FX585 devices can store inter-
nally up to 24,576 single-word instructions and
PIC18FX680 devices can store up to 32,768 single-word
instructions.
The Reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
Figure 4-1 shows the program memory map for
PIC18F6585/8585 devices while Figure 4-2 shows the
program memory map for PIC18F6680/8680 devices.
4.1.1
PIC18F8X8X PROGRAM MEMORY
MODES
PIC18F8X8X devices differ significantly from their
PIC18 predecessors in their utilization of program
memory. In addition to available on-chip Flash program
memory, these controllers can also address up to
2 Mbytes of external program memory through the
external memory interface. There are four distinct
operating modes available to the controllers:
• Microprocessor (MP)
• Microprocessor with Boot Block (MPBB)
• Extended Microcontroller (EMC)
• Microcontroller (MC)
The Program Memory mode is determined by setting
the two Least Significant bits of the CONFIG3L config-
uration byte, as shown in Register 4-1. (See also
Section 24.1 “Configuration Bits” for additional
details on the device configuration bits.)
The Program Memory modes operate as follows:
• The Microprocessor Mode permits access only
to external program memory; the contents of the
on-chip Flash memory are ignored. The 21-bit
program counter permits access to a 2-MByte
linear program memory space.
• The Microprocessor with Boot Block Mode
accesses on-chip Flash memory from addresses
000000h to 0007FFh. Above this, external
program memory is accessed all the way up to
the 2-MByte limit. Program execution auto-
matically switches between the two memories as
required.
• The Microcontroller Mode accesses only
on-chip Flash memory. Attempts to read above
the physical limit of the on-chip Flash (0BFFFh for
the PIC18F8585, 0FFFFh for the PIC18F8680)
causes a read of all ‘0’s (a NOP instruction).
The Microcontroller mode is the only operating
mode available to PIC18F6X8X devices.
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip Flash memory; above
this, the device accesses external program mem-
ory up to the 2-MByte program space limit. As
with Boot Block mode, execution automatically
switches between the two memories as required.
In all modes, the microcontroller has complete access
to data RAM and EEPROM.
Figure 4-3 compares the memory maps of the different
Program Memory modes. The differences between on-
chip and external memory access limitations are more
fully explained in Table 4-1.
 2004 Microchip Technology Inc.
DS30491C-page 51