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PIC18F6585 Datasheet, PDF (442/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module | |||
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PIC18F6585/8585/6680/8680
FIGURE 27-18:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit 6 - - - - - -1
LSb
75, 76
77
SDI
MSb In
bit 6 - - - -1
LSb In
74
Note: Refer to Figure 27-5 for load conditions.
TABLE 27-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS â to SCK â or SCK â Input
TSSL2SCL
TCY
â
71
TSCH
SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 â
71A
Single Byte
40
â
72
TSCL
SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 â
72A
Single Byte
40
â
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 â
74
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
â
75
TDOR
SDO Data Output Rise Time
PIC18FXX8X
â
25
PIC18LFXX8X
45
76
TDOF
SDO Data Output Fall Time
â
25
77
TSSH2DOZ SS â to SDO Output High-Impedance
10
50
78
TSCR
SCK Output Rise Time
(Master mode)
PIC18FXX8X
â
25
PIC18LFXX8X
â
45
79
TSCF
SCK Output Fall Time (Master mode)
â
25
80
TSCH2DOV, SDO Data Output Valid after SCK
PIC18FXX8X
â
50
TSCL2DOV Edge
PIC18LFXX8X
â
100
82
TSSL2DOV SDO Data Output Valid after SS â
PIC18FXX8X
â
50
Edge
PIC18LFXX8X
â
100
83
TSCH2SSH, SS â after SCK Edge
TSCL2SSH
1.5 TCY + 40 â
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS30491C-page 440
 2004 Microchip Technology Inc.
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