PIC18F6585 Datasheet, PDF (343/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
23.14.2 ACKNOWLEDGE ERROR
In the Acknowledge field of a message, the transmitter
checks if the Acknowledge slot (which was sent out as
a recessive bit) contains a dominant bit. If not, no other
node has received the frame correctly. An Acknowl-
edge error has occurred; an error frame is generated
and the message will have to be repeated.
23.14.3 FORM ERROR
If a node detects a dominant bit in one of the four
segments, including end of frame, interframe space,
Acknowledge delimiter, or CRC delimiter, then a form
error has occurred and an error frame is generated.
The message is repeated.
23.14.4 BIT ERROR
A bit error occurs if a transmitter sends a dominant bit
and detects a recessive bit, or if it sends a recessive bit
and detects a dominant bit, when monitoring the actual
bus level and comparing it to the just transmitted bit. In
the case where the transmitter sends a recessive bit
and a dominant bit is detected during the arbitration
field and the Acknowledge slot, no bit error is
generated because normal arbitration is occurring.
23.14.5 STUFF BIT ERROR
lf between the start of frame and the CRC delimiter, six
consecutive bits with the same polarity are detected,
the bit stuffing rule has been violated. A stuff bit error
occurs and an error frame is generated. The message
is repeated.
23.14.6 ERROR STATES
Detected errors are made public to all other nodes via
error frames. The transmission of the erroneous mes-
sage is aborted and the frame is repeated as soon as
possible. Furthermore, each CAN node is in one of the
three error states “error-active”, “error-passive” or “bus-
off” according to the value of the internal error counters.
The error-active state is the usual state where the bus
node can transmit messages and activate error frames
(made of dominant bits) without any restrictions. In the
error-passive state, messages and passive error
frames (made of recessive bits) may be transmitted.
The bus-off state makes it temporarily impossible for
the station to participate in the bus communication.
During this state, messages can neither be received
nor transmitted.
23.14.7 ERROR MODES AND ERROR
COUNTERS
The PIC18F6585/8585/6680/8680 devices contain two
error counters: the Receive Error Counter
(RXERRCNT), and the Transmit Error Counter
(TXERRCNT). The values of both counters can be read
by the MCU. These counters are incremented or
decremented in accordance with the CAN bus
specification.
The PIC18F6585/8585/6680/8680 devices are error-
active if both error counters are below the error-passive
limit of 128. They are error-passive if at least one of the
error counters equals or exceeds 128. They go to bus-
off if the transmit error counter equals or exceeds the
bus-off limit of 256. The devices remain in this state
until the bus-off recovery sequence is received. The
bus-off recovery sequence consists of 128 occurrences
of 11 consecutive recessive bits (see Figure 23-7).
Note that the CAN module, after going bus-off, will
recover back to error-active without any intervention by
the MCU if the bus remains Idle for 128 x 11 bit times.
If this is not desired, the error Interrupt Service Routine
should address this. The current Error mode of the
CAN module can be read by the MCU via the
COMSTAT register.
Additionally, there is an error state warning flag bit,
EWARN, which is set if at least one of the error
counters equals or exceeds the error warning limit of
96. EWARN is reset if both error counters are less than
the error warning limit.
 2004 Microchip Technology Inc.
DS30491C-page 341