PIC18F6585 Datasheet, PDF (124/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
REGISTER 9-12:
IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
IRXIP
R/W-1
WAKIP
R/W-1
ERRIP
R/W-1
TXB2IP/
TXBnIP
R/W-1 R/W-1
TXB1IP⁽¹⁾ TXB0IP⁽¹⁾
bit 7
R/W-1
RXB1IP/
RXBnIP
R/W-1
RXB0IP/
FIFOWMIP
bit 0
bit 7
IRXIP: CAN Invalid Received Message Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
WAKIP: CAN bus Activity Wake-up Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
ERRIP: CAN bus Error Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
When CAN is in Mode 0:
TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
TXBnIP: CAN Transmit Buffer Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit⁽¹⁾
1 = High priority
0 = Low priority
bit 2
TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit⁽¹⁾
1 = High priority
0 = Low priority
bit 1
When CAN is in Mode 0:
RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1 or 2:
RXBnIP: CAN Receive Buffer Interrupts Priority bit
1 = High priority
0 = Low priority
bit 0
When CAN is in Mode 0:
RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIP: FIFO Watermark Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS30491C-page 122
 2004 Microchip Technology Inc.