PIC18F6585 Datasheet, PDF (256/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
19.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 19-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 19-1 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is based
on the following application system assumptions:
CHOLD
= 120 pF
Rs
= 2.5 kΩ
Conversion Error ≤ 1/2 LSb
VDD
= 5V → Rss = 7 kΩ
Temperature
= 50°C (system max.)
VHOLD
= 0V @ time = 0
19.2 A/D VREF+ and VREF- References
If external voltage references are used instead of the
internal AVDD and AVSS sources, the source impedance
of the VREF+ and VREF- voltage sources must be consid-
ered. During acquisition, currents supplied by these
sources are insignificant. However, during conversion,
the A/D module sinks and sources current through the
reference sources. The effect of this current, as specified
in parameter A50, along with source impedance must be
considered to meet specified A/D resolution.
Note:
When using external voltage references
with the A/D converter, the source imped-
ance of the external voltage references
must be less than 20Ω to obtain the spec-
ified A/D resolution. Higher reference
source impedances will increase both
offset and gain errors. Resistive voltage
dividers will not provide a sufficiently low
source impedance.
To maintain the best possible performance
in A/D conversions, external VREF inputs
should be buffered with an operational
amplifier or other low output impedance
circuit.
EQUATION 19-1: ACQUISITION TIME
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
EQUATION 19-2: A/D MINIMUM CHARGING TIME
VHOLD = (VREF – (VREF/2048)) • (1 – e^{(-Tc/CHOLD(RIC + RSS + RS))})
or
TC
= -(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
EXAMPLE 19-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ = TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ = 2 µs + TC + [(Temp – 25°C)(0.05 µs/°C)]
TC
= -CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)
-120 pF (10.5 kΩ) ln(0.0004885)
-1.26 µs (-7.6241)
9.61 µs
TACQ = 2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C)]
11.61 µs + 1.25 µs
12.86 µs
DS30491C-page 254
 2004 Microchip Technology Inc.