PIC18F6585 Datasheet, PDF (433/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
TABLE 27-9: PROGRAM MEMORY READ TIMING REQUIREMENTS (VDD = 4.2 TO 5.5V)
Param.
No
Symbol
Characteristics
Min
Typ
Max
Units
150 TADV2ALL Address Out Valid to ALE ↓ (address
setup time)
0.25 TCY – 10
—
—
ns
151 TALL2ADL ALE ↓ to Address Out Invalid (address
hold time)
5
—
—
ns
155 TALL2OEL ALE ↓ to OE ↓
10
0.125 TCY
—
ns
160 TADZ2OEL AD High-Z to OE ↓ (bus release to OE)
0
—
—
ns
161 TOEH2ADD OE ↑ to AD Driven
0.125 TCY – 5
—
—
ns
162 TADV2OEH LS Data Valid before OE ↑ (data setup time)
20
—
—
ns
163 TOEH2ADL OE ↑ to Data In Invalid (data hold time)
0
—
—
ns
164 TALH2ALL ALE Pulse Width
—
0.25 TCY
—
ns
165 TOEL2OEH OE Pulse Width
0.5 TCY – 5 0.5 TCY
—
ns
166 TALH2ALH ALE ↑ to ALE ↑ (cycle time)
—
1 TCY
—
ns
167 TACC
Address Valid to Data Valid
0.75 TCY – 25
—
—
ns
168 TOE
OE ↓ to Data Valid
—
0.5 TCY – 25 ns
169 TALL2OEH ALE ↓ to OE ↑
0.625 TCY – 10 — 0.625 TCY + 10 ns
171 TALH2CSL Chip Select Active to ALE ↓
—
—
10
ns
171A TUBL2OEH AD Valid to Chip Select Active
0.25 TCY – 20
—
—
ns
FIGURE 27-9:
PROGRAM MEMORY WRITE TIMING DIAGRAM
OSC1
A<19:16>
BA0
AD<15:0>
ALE
CE
WRH or
WRL
UB or
LB
Q1
Q2
Address
150
151
171
171A
157
Q3
Q4
Address
166
Data
153
156
154
Q1
Q2
Address
Address
157A
 2004 Microchip Technology Inc.
DS30491C-page 431