PIC18F6585 Datasheet, PDF (169/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
15.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18FXX80/XX85 devices contain a total of two CCP
modules: CCP1 and CCP2. CCP1 is an enhanced
version of the CCP2 module. CCP1 is fully backward
compatible with the CCP2 module.
The CCP1 module differs from CCP2 in the following
respect:
• CCP1 contains a special trigger event that may
reset Timer1 or the Timer3 register pair
• CCP1 contains “CAN Message Time-Stamp Trigger”
• CCP1 contains enhanced PWM output with
programmable dead band and auto-shutdown
functionality
Additionally, the CCP2 special event trigger may be
used to start an A/D conversion if the A/D module is
enabled.
To avoid duplicate information, this section describes
basic CCP module operation that applies to both CCP1
and CCP2. Enhanced CCP functionality of the
CCP1 module is described in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
The control registers for the CCP1 and CCP2 modules
are shown in Register 15-1 and Register 15-2,
respectively. Table 15-2 details the interactions of the
CCP and ECCP modules.
REGISTER 15-1:
CCP1CON REGISTER
R/W-0 R/W-0 R/W-0
P1M1
P1M0 DC1B1
bit 7
R/W-0
DC1B0
R/W-0
CCP1M3
R/W-0 R/W-0
CCP1M2 CCP1M1
R/W-0
CCP1M0
bit 0
bit 7-6
bit 5-4
bit 3-0
P1M1:P1M0: Enhanced PWM Output Configuration bits
If CCP1M<3:2> = 00, 01, 10:
xx =P1A assigned as capture/compare input; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11:
00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as
port pins
11 = Full-bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are
found in CCPR1L.
CCP1M3:CCP1M0: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP pin low, on compare match force CCP pin high
1001 = Compare mode, initialize CCP pin high, on compare match force CCP pin low
1010 = Compare mode, generate software interrupt only, CCP pin is unaffected
1011 = Compare mode, trigger special event, resets TMR1 or TMR3
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
 2004 Microchip Technology Inc.
DS30491C-page 167