PIC18F6585 Datasheet, PDF (131/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
FIGURE 10-6:
BLOCK DIAGRAM OF RB2:RB0 PINS
RBPU⁽²⁾
Data Bus
WR Port
WR TRIS
Data Latch
DQ
CK
TRIS Latch
DQ
CK
VDD
P
Weak
Pull-up
I/O pin⁽¹⁾
TTL
Input
Buffer
RD TRIS
RD Port
QD
EN
INTx
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 10-7:
BLOCK DIAGRAM OF RB3 PIN
RBPU⁽²⁾
CCP2MX
CCP Output⁽³⁾
Enable⁽³⁾
CCP Output
Data Bus
WR LATB or
WR PORTB
WR TRISB
RD TRISB
RD LATB
RD PORTB
1
0
Data Latch
DQ
CK
TRIS Latch
D
CK _Q
Q
D
EN
VDD
P
Weak
Pull-up
VDD
P
N
VSS
TTL
Input
Buffer
I/O pin⁽¹⁾
RD PORTB
CCP2 or INT3
Schmitt Trigger
Buffer
CCP2MX = 0
Note 1:
2:
3:
I/O pin has diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
For PIC18FXX85 parts, the CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration
register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.
 2004 Microchip Technology Inc.
DS30491C-page 129