PIC18F6585 Datasheet, PDF (21/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X8X
PIC18F8X8X
Pin
Type
TQFP PLCC TQFP
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/CANTX1
RG0
CANTX1
3
12
5
I/O
ST
Digital I/O.
O
TTL
CAN bus transmit 1.
RG1/CANTX2
RG1
CANTX2
4
13
6
I/O
ST
Digital I/O.
O
TTL
CAN bus transmit 2.
RG2/CANRX
RG2
CANRX
5
14
7
I/O
ST
Digital I/O.
I
TTL
CAN bus receive.
RG3
RG3
6
15
8
I/O
ST
Digital I/O.
RG4/P1D
RG4
P1D
8
17
10
I/O
ST
Digital I/O.
O
TTL
ECCP1 PWM output D.
RG5
7
16
9
I
ST
General purpose input pin.
Legend: TTL
ST
I
P
= TTL compatible input
= Schmitt Trigger input with CMOS levels
= Input
= Power
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX
configuration bit.
 2004 Microchip Technology Inc.
DS30491C-page 19