PIC18F6585 Datasheet, PDF (475/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
INDEX
A
A/D .................................................................................... 249
A/D Converter Interrupt,
Configuring ....................................................... 253
Acquisition Requirements ......................................... 254
Acquisition Time........................................................ 254
ADCON0 Register..................................................... 249
ADCON1 Register..................................................... 249
ADCON2 Register..................................................... 249
ADRESH Register..................................................... 249
ADRESH/ADRESL Registers ................................... 252
ADRESL Register ..................................................... 249
Analog Port Pins ....................................................... 152
Analog Port Pins,
Configuring ....................................................... 255
Associated Register
Summary .......................................................... 257
Automatic Acquisition Time....................................... 255
Calculating Minimum Required
Acquisition Time (Example) .............................. 254
CCP2 Trigger ............................................................ 256
Configuring the Module............................................. 253
Conversion Clock (TAD) ............................................ 255
Conversion Requirements ........................................ 447
Conversion Status
(GO/DONE Bit) ................................................. 252
Conversions .............................................................. 256
Converter Characteristics ......................................... 446
Minimum Charging Time........................................... 254
Special Event Trigger
(CCP) ................................................................ 171
Special Event Trigger
(CCP2) .............................................................. 256
VREF+ and VREF- References ................................... 254
Absolute Maximum Ratings .............................................. 413
AC (Timing) Characteristics .............................................. 426
Load Conditions for Device
Timing Specifications ........................................ 427
Parameter Symbology .............................................. 426
Temperature and Voltage
Specifications.................................................... 427
Timing Conditions ..................................................... 427
ACKSTAT Status Flag ...................................................... 219
ADCON0 Register............................................................. 249
GO/DONE Bit............................................................ 252
ADCON1 Register............................................................. 249
ADCON2 Register............................................................. 249
ADDLW ............................................................................. 371
ADDWF ............................................................................. 371
ADDWFC .......................................................................... 372
ADRESH Register............................................................. 249
ADRESH/ADRESL Registers ........................................... 252
ADRESL Register ............................................................. 249
Analog-to-Digital Converter.
See A/D.
ANDLW............................................................................. 372
ANDWF............................................................................. 373
Assembler
MPASM Assembler .................................................. 407
Auto-Wake-up on Sync
Break Character ....................................................... 242
B
Baud Rate Generator ....................................................... 215
BC..................................................................................... 373
BCF .................................................................................. 374
BF Status Flag .................................................................. 219
Bit Timing Configuration Registers
BRGCON1................................................................ 340
BRGCON2................................................................ 340
BRGCON3................................................................ 340
Block Diagrams
16-bit Byte Select Mode ............................................. 98
16-bit Byte Write Mode ............................................... 96
16-bit Word Write Mode.............................................. 97
A/D............................................................................ 252
Analog Input Model................................................... 253
Baud Rate Generator ............................................... 215
CAN Buffers and Protocol Engine ............................ 276
Capture Mode Operation .......................................... 170
Comparator
Analog Input Model .......................................... 263
Comparator I/O Operating Modes
(diagram) .......................................................... 260
Comparator Output................................................... 262
Comparator Voltage Reference................................ 266
Compare Mode Operation ................................ 171, 176
Enhanced PWM........................................................ 178
Low-Voltage Detect (LVD)........................................ 270
Low-Voltage Detect (LVD) with
External Input ................................................... 270
MSSP (I²C Master Mode)......................................... 213
MSSP (I²C Mode)..................................................... 198
MSSP (SPI Mode) .................................................... 189
On-Chip Reset Circuit................................................. 33
PIC18F6X8X Architecture .......................................... 10
PIC18F8X8X Architecture .......................................... 11
PLL ............................................................................. 25
PORT/LAT/TRIS Operation ...................................... 125
PORTA
RA3:RA0 and RA5 Pins.................................... 126
RA4/T0CKI Pin ................................................. 126
RA6 Pin (When Enabled as I/O)....................... 126
PORTB
RB2:RB0 Pins................................................... 129
RB3 Pin ............................................................ 129
RB7:RB4 Pins................................................... 128
PORTC (Peripheral Output
Override)........................................................... 131
PORTD and PORTE
(Parallel Slave Port).......................................... 152
 2004 Microchip Technology Inc.
DS30491C-page 473