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PIC18F6585 Datasheet, PDF (403/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module | |||
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PIC18F6585/8585/6680/8680
SUBLW
Subtract W from literal
Syntax:
[ label ] SUBLW k
Operands:
0 ⤠k ⤠255
Operation:
k â (W) â W
Status Affected: N, OV, C, DC, Z
Encoding:
0000 1000 kkkk kkkk
Description:
W is subtracted from the eight-bit
literal âkâ. The result is placed in
W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
literal âkâ
Q3
Process
Data
Q4
Write to W
Example 1:
SUBLW 0x02
Before Instruction
W= 1
C= ?
After Instruction
W= 1
C = 1 ; result is positive
Z=0
N= 0
Example 2:
SUBLW 0x02
Before Instruction
W= 2
C= ?
After Instruction
W=
C=
Z=
N=
0
1 ; result is zero
1
0
Example 3:
SUBLW 0x02
Before Instruction
W= 3
C= ?
After Instruction
W=
C=
Z=
N=
FF ; (2âs complement)
0 ; result is negative
0
1
SUBWF
Subtract W from f
Syntax:
[ label ] SUBWF f [,d [,a]]
Operands:
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
Operation:
(f) â (W) â dest
Status Affected: N, OV, C, DC, Z
Encoding:
0101 11da ffff ffff
Description:
Subtract W from register âfâ (2âs
complement method). If âdâ is â0â,
the result is stored in W. If âdâ is
â1â, the result is stored back in
register âfâ (default). If âaâ is â0â, the
Access Bank will be selected,
overriding the BSR value. If âaâ is
â1â, then the bank will be selected
as per the BSR value (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example 1:
SUBWF REG, 1, 0
Before Instruction
REG
W
C
=3
=2
=?
After Instruction
REG
W
C
Z
N
=1
=2
=1
=0
=0
; result is positive
Example 2:
SUBWF REG, 0, 0
Before Instruction
REG
W
C
=2
=2
=?
After Instruction
REG
W
C
Z
N
=2
=0
=1
=1
=0
; result is zero
Example 3:
SUBWF REG, 1, 0
Before Instruction
REG
W
C
=1
=2
=?
After Instruction
REG
W
C
Z
N
= FFh ;(2âs complement)
=2
= 0 ; result is negative
=0
=1
 2004 Microchip Technology Inc.
DS30491C-page 401
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