SDA55XX Datasheet, PDF (99/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Power Saving modes
8
Power Saving modes
The controller provides four modes in which power consumption can be significantly
reduced.
• Idle mode: The CPU is gated off from the oscillator. All peripherals except WDT(in
watch dog mode) are still provided with the clock and are able to work.
• Power-down mode: Operation of the controller is turned off. This mode is used to save
the contents of internal RAM with a very low standby current.
• Power save mode: In this mode display generator, Slicer_acq_sync, VADC, CADC,
ADC_wakeup, PWM, CRT, WDT, DAC, PLL, and Display(display, pixel clock and D
sync) can be turned off.
• Slow down mode: In this mode the system frequency is reduced by one fourth.
All modes are entered by software. Special function register is used to enter one of these
modes.
8.1
Power Save mode registers
Default after reset: 00_h PSAVE bit addressable SFR-Address D8_H
(MSB)
--
--
--
CADC WAKUP SLI_ACQ DISP
(LSB)
PERI

&$'&
:$.83
1RW XVHG
&RQWUROOHU $'&
0: Power save Mode not started
1: Power save Mode started
In Power save mode all 4 controller ADC channels are disabled.
:DNH XS RI &$'&
0: Power save Mode not started
1: Power save Mode started
In Power save mode ADC wake up unit of CADC is disabled.
Note that Power save mode of wake up unit is only useful in saving
power when CADC bit is set.
Semiconductor Group
99
User’s Manual July 99