SDA55XX Datasheet, PDF (124/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
General Purpose Timers/Counters
12.1.4 Timer/Counter Control Register
Default after reset: 00_H
(MSB)
7&21
SFR-Address 88_H
(LSB)
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
7)
Timer 1 overflow flag. Set by hardware on timer/counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
75
Timer 1 run control bit. Set/cleared by software to turn timer/
counter on/off.
7)
Timer 0 overflow flag. Set by hardware on timer/counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
75
Timer 0 run control bit. Set/cleared by software to turn timer/counter
on/off.
,(
Interrupt 1 edge flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
,7
Interrupt 1 type control bit. Set/cleared by software to specify edge/
low level triggered external interrupts.
,(
Interrupt 0 edge flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
,7
Interrupt 0 type control bit. Set/cleared by software to specify edge/
low level triggered external interrupts.
Semiconductor Group
124
User’s Manual July 99