SDA55XX Datasheet, PDF (93/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Interrupts
7.8
Interrupt and memory extension
When an interrupt occurs, the Memory Management Unit (MMU) carries out the following
sequence of actions:
1. The MEX1 register bits are made available on SDATAO [7:0].
2. The MEXSP register bits are made available on SADD[7:0].
3. The Stack read and write signals are set for a write operation.
4. A write is performed to External memory.
5. The MEXSP Stack Pointer is incremented.
6. The Interrupt Bank bits IB19 - IB16 (MEX2.3 - MEX2.0) are copied to both the NB19
- NB16 and the CB19 - CB16 bits in the MEX1.
Then on return from the interrupt service routine:
1. The MEXSP Stack Pointer is decremented.
2. The MEXSP register bits are made available on SADD [7:0].
3. The Stack read and write signals are set for a read operation.
4. A read is performed on External memory.
5. SDATAI [7:0] is copied to the MEX1 register.
This action allows the user to place interrupt service routines on specific banks.
7.9
Interrupt Handling
Exteranl interrupt 0, external interrupt 1, timer 0, timer 1 abd UART interrupt are handled
as following.
Interrupts are sampled at S5P2 in each machine cycle and the sampled interrupts polled
during the following machine cycle. If an interrupt is set when it is sampled, it will be
serviced provided:
• An interrupt of an equal or higher priority is not currently being serviced
• The polling cycle is not the final cycle of a multi-cycle instruction, and
• The current instruction is neither a RETI nor a write either to one of Interrupt Enable
registers or to one of the Interrupt Priority registers.
Semiconductor Group
93
User’s Manual July 99