SDA55XX Datasheet, PDF (100/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Power Saving modes
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0: Power save Mode not started
1: Power save Mode started
In Power save mode Video A to D, Slicer , sync unit and acquisition
are disabled. All the pending bus requests are masked off.
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0: Power save Mode not started
1: Power save Mode started
In Power save mode display generator, pixel clock unit ,display
sync unit , sandcastle decoder and COR_BLA are disabled. All the
pending bus request are masked off.
DAC is also switched off and it outputs the values defined for DAC
off. COR_BLA output their reset value.
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0: Power save Mode not started
1: Power save Mode started
In Power save mode WDT (in timer mode), PWM and CRT are
disabled. It is only possible to enterthis power save mode if
watchdog is not started in a watchdog mode.
Default after reset: 00_h PSAVEX bit addressable SFR-Address D7_H
(MSB)
--
--
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--
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Clk_Src PLL_rst
(LSB)
PLLS

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0: 200 Mhz PLL (33.33Mhz system clock) selected.
1: PLL is bypassed oscillator clock 6 MHz (3Mhz system clock
selected)
In this mode slicer, acquisition, DAC and display generator are
disabled.
Semiconductor Group
100
User’s Manual July 99