SDA55XX Datasheet, PDF (154/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Sync System
EVCR BVCR
H-Sync Delay
(SDH)
Vertical Blacklevel Clamping
Border
Character Display Area
V-Sync
Delay
(SDV)
VLR
Variable
Height
(25 rows)
Variable count of character columns (33..64)
t_{H_clmp_e}
(EHCR)
t_{H_clmp_b}
(BHCR)
H-Sync
Figure 16
t_{H-period (HPR)}
TVTpro’s Display Timing
Blacklevel Clamping Area
During horizontal and vertical blacklevel clamping, the black value (RGB = 000)
is delivered on output side of TVTpro. Inside this area the BLANK pin and COR
pin are set to the same values which are defined as transparency for subCLUT0
(see also 18.4.7). This area is programmable in vertical direction (in terms of
lines) and in horizontal direction in terms of 33.33 MHz clock cycles.
Border Area
The size of this area is defined by the sync delay registers (SDH and SDV) and
the size of the character display area. The color and transparency of this area
is defined by a color look up vector (see also 18.4.3).
Semiconductor Group
154
User’s Manual July 99