SDA55XX Datasheet, PDF (109/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Memory Organization
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The stack can be located anywhere in the internal data RAM address space. The stack
depth is limited only by the available internal data RAM, thanks to an 8-bit re-locatable
stack pointer. The stack is used for storing the program counter during subroutine calls
and may also be used for passing parameters. Any byte of internal data RAM or special
function registers accessible through direct addressing can be pushed/popped. By
default Stack Pointer always has a reset value of 07_h.
10.2.2 Extended Data RAM(XRAM)
An additional on-chip RAM space called ‘XRAM’ extends the internal RAM capacity. Up
to 16 Kilobytes of XRAM are accessed by MOVX @DPTR. XRAM is located in the upper
area of the 64K address space.
1 Kbyte of the XRAM, called VBI Buffer, is reserved for storing teletext data. 1KByte of
address space can be allocated for CPU work space. Three Kilobyte of RAM is reserved
as Display RAM. Rest of the RAM can be configured between Teletext page memory
and DRCS (Dynamically Redefinable Character Set) memory.
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XRAM is mapped in the address space of C000_h to FFFF_h. 16 KBytes are implemented
on Chip the address space of the 16K block is decoded starting from C000h. Note that
this decoding is done independent of the memory banking. That means that in all 16
banks of 64K, upper 16K address space is reserved for internal Extended data memory.
This decoding method has an advantage,while copying data backand forth from on-chip
RAMand off-chip RAM, there is no need to switch the memory banks.
10.3
Memory Extension
The controller provides four additional address lines A16, A17, A18 and A19. These
additional address lines are used to access program and data memory space up to
1MByte. The extended memory space is split into 16 banks of 64Kbyte each.
A16 is available as a dedicated pin, however A17, A18 and A19 work as alternate func-
tion to port pins P4.0, P4.1 and P4.4 respectively. Refer to register CSCR 1(A19_P4_4,
A18_P4_1,A17_P4_0).
Semiconductor Group
109
User’s Manual July 99