SDA55XX Datasheet, PDF (43/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Slicer and Acquisition
FC3
This 16-bit framing code is loaded with the field parameters as well as a don’t care mask.
The incoming signal is compared with both, framing code and don’t care mask. Further
reception is enabled if all bits which are not don’t care match the incoming data stream.
FCWSS
This FC is fixed to that of WSS. Only an error free signal will enable the reception of the
WSS data line.
FC-Check Select
There is a two bit line parameter called FCSEL. By means of this parameter the user will
be able to select which FC-Check is used for the actual line. If NORM is set to WSS the
WSS FCcheck is used independently of FCSEL.
5.4.2 Interrupts
Some events which occur inside the slicer, sync separation or acquisition interface
should cause an interrupt. They are summarized in register CISR0 and CISR1. The
hardware sets the associated interrupt flag which must be manually reset by software
before the next interrupt can be accepted.
5.4.3 VBI Buffer and Memory Organization
Slicer and acquisition interface need parameters for configuration and produce status
information for the CPU.
Some of these parameters and status bits are constant for a field. Those parameters are
called field parameters. They are downloaded after the vertical sync.
Other parameters and status bits may change from line to line (e.g. data service
depending values). Those parameters are called line parameters. They are downloaded
after each horizontal sync impulse.
The start address of the VBI buffer can be configured with a special function register
’STRVBI’. 9 bytes are needed for the field parameter. 47 byte should be reserved for
every sliced data line. If 18 lines of data (in full channel mode 314) have been send to
memory no further acquisition takes place until the next vertical pulse appears and the
H-PLL is still locked. That means if at least 855 Bytes (14767 Bytes in full channel mode)
are reserved for the VBI buffer no VBI overflow is possible. The acquisition can be
started and stopped by the controller using bit ’ACQON’ of register STRVBI. The
acquisition is stopped as soon as this bit changed to ’0’. If the bit is changed back to ’1’
the acquisition starts again with the next V-pulse (only if STAB=1). The start address (Bit
Semiconductor Group
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User’s Manual July 99