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| SDA55XX Datasheet, PDF (169/230 Pages) Infineon Technologies AG – Preliminary & Confidential | |||
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SDA 55xx
Preliminary & Confidential
Reset: 00h
(MSB)
-
-
-
%9&5
-
-
Sync System
SFR Address EAH
(LSB)
-
BVCR(9) BVCR(8)
Reset: 00h
(MSB)
%9&5
SFR Address EBH
(LSB)
BVCR(7) BVCR(6) BVCR(5) BVCR(4) BVCR(3) BVCR(2) BVCR(1) BVCR(0)
Bit
Function
BVCR (9...0) Beginning of Vertical Clamp Phase. (Master and slave mode).
This register defines the beginning of the vertical clamp phase from the
positive edge of the vertical sync impulse (at normal polarity) in count of
lines.
If EVCR is smaller than BVCR than the clamp phase will appear during
Vsync.
Reset: 00h
(MSB)
(9&5
SFR Address ECH
(LSB)
-
-
-
-
-
-
EVCR(9) EVCR(8)
Reset: 04h
(MSB)
(9&5
SFR Address EDH
(LSB)
EVCR(7) EVCR(6) EVCR(5) EVCR(4) EVCR(3) EVCR(2) EVCR(1) EVCR(0)
Bit
Function
EVCR (9...0)
End of Vertical Clamp Phase. (Master and slave mode).
This register defines the end of the vertical clamp phase from the positive
edge of the vertical sync impulse (at normal polarity) in count of lines.
If EVCR is set to a value smaller than BVCR than the vertical blanking
phase will last over the vertical blanking interval.
If EVCR is smaller than BVCR than the clamp phase will appear during
Vsync.
Semiconductor Group
169
Userâs Manual July 99
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