SDA55XX Datasheet, PDF (127/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Capture reload timer
In capture mode if REL bit is set counter is automatically reloaded upon event with the
reload value and starts to count. If however REL bit is not set then counter continues to
count from the current value.
OV bit is not effected by the capture event..
Note:1) Min_cap register has no functionality in this mode.
Note 2) Interrupt would be generated from CRT, however it will only be registered in the
int source register if intsrc bits in the CSCR1are appropriately set. It is not required to
use the CRT generated interrupt in this mode. Direct pin interrupt can be used.
13.3.7 Polling mode
Polling mode is started by setting the PLG bit, PLG= 1 (START bit is in don’t care for this
mode) Setting RUN bit will reload the counter with reload value and reset the overflow
bit and start the counting.
In the timer polling mode, capture register mirrors the current timer value, note that in
this mode any event at selected port pin is ignored. Upon overflow OV bit is set.
Note 1) Interrupts are not generated as events are not recognized.
13.3.8 Capture mode with spike suppression at the start of a telegram
This mode is specially been implemented to prevent false interrupt from being generated
specially in idle mode while waiting for a new infra red telegram.
This mode is entered by setting the START bit (PLG =0). Software sets Start bit to
indicate it is expecting a new telegram. Setting RUN bit will reload the counter with reload
value and reset the overflow bit and start the counting.
13.3.9 First event
On occurrence of capture event, counter value is captured and comparator then sets the
First bit. Interrupt is suppressed. OV bit is reset and counter reloads the reload value
(regardless of the status of REL bit) and starts counting again.
13.3.10 Second event
On occurrence of second capture event, counter value is captured and interrupt is
triggered if the capture value exceeds the value in the Min_Cap register and the OV bit
is not set. First bit is reset. Counter will now continue in the normal capture mode.
Software may reset the START bit if the capture value is a valid pulse of a telegram.
If the pulse was invalid then software must stop the counter and start again (Run bit first
reset and then SET) with start bit set to wait for a new telegram.
Semiconductor Group
127
User’s Manual July 99