SDA55XX Datasheet, PDF (55/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Slicer and Acquisition
Default after reset: 00_H
(MSB)
$&4/3
(LSB)
MLENGTH MLENGTH MLENGTH ALENGTH ALENGTH CLKDIV
(2)
(1)
(0)
(1)
(0)
(2)
CLKDIV
(1)
CLKDIV
(0)
CLKDIV(1..0):
The slicing level filter needs to find the DC value of the CVBS during
CRI. In order to do this it should suppress at least the CRI
frequency. As different services use different data frequencies the
CRI frequency will be different as well. Therefore the filter
characteristic needs to be shifted. This can be done by using
different clocks for the filter. The filter itself shows sufficient
suppression for frequencies between 0.0757*SL_CLK and 0.13*SL_CLK
(SL_CLK is the actual filter clock and corresponds to slicer 1)
8GF9DW
000
001
010
011
100
101
110
111
Note: f_s = 33.33MHz
TG_&/.
1*f_s
1/2*f_s
1/3*f_s
1/4*f_s
1/5*f_s
1/6*f_s
1/7*f_s
1/8*f_s
ALENGTH(2..0):
If noise has been detected or if NOISEON=1 the output of the
slicing level filter is further averaged by means of an accumulation
(arithmetic averaging). ALENGTH specifies the number of slicing
level filter output values used for averaging. The accumulation
clock depends on CLKDIV.
$/(1*7+
00
01
10
11
1XPEHU RI 6OLFLQJ /HYHO 2XWSXW
9DOXHV XVHG IRU $YHUDJLQJ
2
4
8
16
Semiconductor Group
55
User’s Manual July 99