SDA55XX Datasheet, PDF (41/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Slicer and Acquisition
Frequency Attenuation
During signal transmission the CVBS is attenuated severely. This attenuation normally
is frequency depending. That means that the higher the frequency the stronger the
attenuation. As the clock-run-in (from now on CRI) for teletext represents the highest
possible frequency (3.5MHz) it can be used to measure the attenuation. As only strong
negative attenuation causes problems during data slicing a flag is needed to notify highly
negative attenuation. If this flag is set a special peaking filter is switched on in the
correcting circuit part.
Group Delay
Quite often the data stream is corrupted because of group delay distortion introduced by
the transmission channel. The teletext framing code (E4_H) is used as a reference for
measurement. The delay of the edges inside this code can be used to measure the group
delay distortion. The measurement is done every teletext line and filtered over several
lines. It can be detected whether the signal has positive, negative or no group delay
distortions. Two flags are set accordingly. By means of this two flags an allpass
contained in the correcting circuit is configured to compensate the positive or negative
group delays.
5.2.2 Data Separation
Parallel to the signal analyses and distortion compensation a filter is calculating the
slicing level. The slicing level is the mean-value of the CRI. As the teletext is coded using
the NRZ format, the slicing level can not be calculated outside the CRI and is therefore
frozen after CRI. Using this slicing level the data is separated from the digital CVBS
signal. The result is a stream of zeros and ones. In order to find the logical zeros and
ones which have been transmitted, the data clock needs to be recovered. Therefore a
digital data PLL (D-PLL) is synchronized to the data clock during CRI using the
transitions in the sliced data stream. This D-PLL is also frozen after CRI.
Timing informations for freezing the slicing level, stopping the D-PLL and other actions
are generated by the timing circuit. It generates all control signals which are
synchronized to the data start.
5.3
H/V-Synchronization
Slicer and acquisition interface need a lot of signals which have to be synchronized to
the incoming CVBS (e.g. line number, field or line start). Therefore a sync slicing level is
calculated and the sync signal is sliced from the filtered digital CVBS signal. Using digital
integration vertical and horizontal sync pulses are separated. The horizontal pulses are
fed into a digital H-PLL which has flywheel functionality. The H-PLL includes a counter
which is used to generate all the necessary horizontal control signals. The vertical sync
Semiconductor Group
41
User’s Manual July 99