SDA55XX Datasheet, PDF (133/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Pulse Width Modulation Unit
14
Pulse Width Modulation Unit
The Pulse Width Modulation unit consists of 6 quasi 8 bit and 2 quasi 14 bit PWM
channels. PWM channels are programmed by special function registers and each
individual channel can be enabled and disabled inindividually.
14.1
Reset Values
All the PWM unit registers PWME, PWCOMP8 0-5, PWCOMP14 0-1,
PWMCOMPEXT14 0-1, PWML and PWMH are by default reseted to 00h.
14.2
Input clock
Input clock to PWMU fpwm is derived from fsys. fsys is 33.33 Mhz in normal mode and
in slowdown mode 8.33 Mhz. In normal mode fsys is divided by 2 and in slow down mode
it is directly fed to the PWMU. Therefore PWM unit is counting at 16.5 Mhz in normal
mode and 8.25 Mhz in slow down mode. If PR bit PCOMPEXT14 0(bit 0) is set the then
the counting frequency is half of that.
In addition PWM_direct bit makes it possible to run PWMcounter at system frequency,
ignoring PR bit and the built in divide by 2 prescaler.
To reduce electromagnetic radiation, the different PWM-channels are not switched on
simultaneously with the same counter value, but delayed each with one clock cycle to
the next channel :
Channel 0 : 0 clock cycles delayed, Channel 1 : 1 clock cycle delayed, .... , Channel 5 :
5 clock cycles, ...... , PWM14_0 : 6 clock cycles, PWM14_1 : 7 clock cycles delayed.
14.3
Port pins
Port 1 is a dual function port. Under normal mode it works as standard port 1, under
alternate function mode it outputs the PWM channels.
P1.0... P1.5 corresponds to the six 8 bit resolution PWM channels PWM8_0...PWM8_5.
P1.6 and P1.7 coressponds to the two 14 bit resolution PWM channels PWM14_0 and
PWM14_1. PWM channels can be indivdually enabled by corresponding bits in the
PWME register provided PWM_Tmr bit is not set (timer mode start bit).
Semiconductor Group
133
User’s Manual July 99