SDA55XX Datasheet, PDF (104/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Power Saving modes
8.3
Power down mode
Entering the power-down mode is done by two consecutive instructions immediately
following each other. The first instruction has to set bit PDE (PCON.1) and must not set
bit PDS (PCON.6). The following instruction has to set bit PDS (PCON.6) and must not
set bit PDE (PCON.1). Bits PDE and PDS will automatically be cleared after having been
set.
This double-instruction sequence is implemented to minimize the chance of
unintentionally entering the power-down mode. The following instruction sequence may
serve as an example:
ORLPCON,#00000010_B
;Set bit PDE, bit PDS must not be set.
ORLPCON,#01000000_B
;Set bit PDS, bit PDE must not be set.
The instruction that sets bit PDS is the last instruction executed before going into power-
down mode.
Concurrent setting of the enable and the start bits does not set the device into the
respective power saving mode.
If idle mode and power-down mode are invoked simultaneously, the power-down mode
takes precedence.
The only exit from power-down mode is a hardware reset. The reset will redefine all
SFRs, but will not change the contents of internal RAM.
8.4
Power save mode
Bits in the PSave register individually enable and disable different major blocks in the IC.
Note that Power save mode is independent of Idle and power down mode. In case of idle
mode, blocks which are in power save mode remains in power save mode.
Entering the power down mode with Power save mode is possible. However leaving the
power down mode (reset) would intialize all the power save register bits.
Note that Power save mode has a higher priority then idle mode.
8.5
Slow down mode
SD bit in PCON register when sets divides the system frequency by 4. During the normal
operation TVT Pro is running with 33.33Mhz and in SD mode TVT Pro runs with
8.33MHZ. In slow down mode the slicer, Acquisiton and display are disabled regardless
of Power save mode or other modes. All the pending request to the bus by these blocks
are masked off. Leaving slow down mode restores the original status of these blocks.
Semiconductor Group
104
User’s Manual July 99