SDA55XX Datasheet, PDF (123/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
General Purpose Timers/Counters
INT1 is not affected by the counter’s operation. If enabled, an interrupt will occur when
the input at INT0 or INT1 is low. The counters are enabled for incrementing when
TCON’s TR1 and TR0 bits are set. When the counters overflow, the TF1 and TF0 bits in
TCON get set, and interrupt requests are generated.
The counter circuitry counts up to all 1’s and then overflows to either 0’s or the reload
value. Upon overflow, TF1 or TF0 is set. When an instruction changes the timer’s mode
or alters its control bits, the actual change occurs at the end of the instruction’s
execution.
12.1.3 Timer/Counter Mode Register
Default after reset: 00_H
(MSB)
GATE
C/T
M1
702'
M0
GATE
C/T
SFR-Address 89_H
(LSB)
M1
M0
Timer 1
Timer 0
*$7(
&7
Gating control when set. Timer/counter ‘x’ is enabled only while
‘INTx’ pin is high and ‘TRx’ control pin is set. When cleared, timer
‘x’ is enabled, whenever ‘TRx’ control bit is set.
Timer or counter selector. Cleared for timer operation (input from
internal system clock). Set for Counter operation (input from ‘Tx’
input pin).
7DEOH 
0 0

0

1

0

1
2SHUDWLQJ 0RGH
SAB 8048 timer: ‘TLx’ serves as five-bit prescaler.
16-bit timer/counter: ‘THx’ and ‘TLx’ are cascaded, there is no prescaler.
8-bit auto-reload timer/counter: ‘THx’ holds a value which is to be
reloaded into ‘TLx’ each time it overflows.
(Timer 0)TL0 is an eight-bit timer/counter controlled by the standard
timer 0 control bits; TH0 is an eight-bit timer only controlled
by timer 1 control bits.
(Timer 1)timer/counter 1 is stopped.
Semiconductor Group
123
User’s Manual July 99