SDA55XX Datasheet, PDF (164/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Bit
Function
Sync System
VLR (9...0)
Amount of Vertical Lines in a Frame. (Master mode only).
TVTpro generates in sync master mode vertical sync impulses. If for
example a normal PAL timing should be generated, set this register to
„625d’ and set the interlace bit to ’0’. The hardware will generate a
vertical impulse periodically after 312.5 lines. If a non-interlace picture
with 312 lines should be generated, set this register to „312’ and set the
interlace bit to ’1’. The hardware will generate a vertical impulse every
312 lines. A progressive timing can be generated by setting VLR to
’625’ and interlace to ’0’.
Semiconductor Group
164
User’s Manual July 99