SDA55XX Datasheet, PDF (96/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Interrupts














/RZ OHYHO
+LJK OHYHO
'LVDEOHG
'LVDEOHG
1HJDWLYH HGJH WULJJHUHG
3RVLWLYH HGJH WULJJHUHG
3RVLWLYH DQG QHJDWLYH HGJH WULJJHUHG
Default after reset: 05_H
(MSB)
EXX1R EXX1F EXX0R
,5&21
EXX0F EX1R
EX1F
SFR Address AD_H
(LSB)
EX0R EX0F
(;;5
(;;)
(;;5
(;;)
(;5
(;)
(;5
(;)
if set, ExternalX 1-interrupt detection on rising edge at Pin P3.7
if set, ExternalX 1-interrupt detection on falling edge at Pin P3.7
if set, ExternalX 0-interrupt detection on rising edge at Pin P3.1
if set, ExternalX 0-interrupt detection on falling edge at Pin P3.1
if set, External 1-interrupt detection on rising edge at Pin P3.3
if set, External 1-interrupt detection on falling edge at Pin P3.3
if set, External 0-interrupt detection on rising edge at Pin P3.2
if set, External 0-interrupt detection on falling edge at Pin P3.2
Development Note: In order to implement the edge triggering functionality, IT0 and IT1
are mirrore outside the core.
Note: if both EXxR and EXxF are set both rising and falling edges would generate
interrupt. Minimmum delay between the interrupts should be ensured by the software.If
both the EXxR and EXxF are reset to 0. Interrupt is disabled.
Note External extra interupts EX1 and EX2 are edge triggered interrupts only.
Note:When int0 or int1 is used together with capture reload timer, it is possible to
generate interupt through CRT. For further details refer to the chapter CRT.
Semiconductor Group
96
User’s Manual July 99