SDA55XX Datasheet, PDF (108/230 Pages) Infineon Technologies AG – Preliminary & Confidential

Preliminary & Confidential
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SDA 55xx
Memory Organization
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10.2
Internal Data RAM
Internal Data RAM is split into CPU RAM and XRAM
10.2.1 CPU RAM
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The internal CPU RAM (IRAM) occupies address space 00_h to FF_h. This space is further split into
two where lower 128 Bytes (00_h--7F_h) can be accessed using both direct and indirect register
addressing method. Upper half 128 Bytes (80_h-FF_h) can be accessed using register indirect method
only. Register direct method for this address space (80_h--FF_h) is reserved for Special function
register access.
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Controller registers are also located in IRAM. Four banks of eight registers each occupy
locations 0 through 31. Only one of these banks may be enabled at a time through a two-
bit field in the PSW.
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128-bit locations of the on-chip RAM are accessible through direct addressing.These bits
reside in internal data RAM at byte locations 32 through 47.
Semiconductor Group
108
User’s Manual July 99