SDA55XX Datasheet, PDF (148/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Analog Digital Converter (CADC)
Default after reset: 00_H
(MSB)
&$'&
SFR-Address D2
(LSB)
CADC1(7) CADC1(6) CADC1(5) CADC1(4) CADC1(3) CADC1(2) CADC1(1) CADC1(0)
CADC1(7..0):
ADC result of channel 2
After finishing the A to D conversion the processor is informed by
means of an interrupt. The interrupt service routine can now take
the conversion result of channel 2from CADC1. The result will be
available for about 46µs after the interrupt.
Default after reset: 00_H
(MSB)
&$'&
SFR-Address D3
(LSB)
CADC2(7) CADC2(6) CADC2(5) CADC2(4) CADC2(3) CADC2(2) CADC2(1) CADC2(0)
CADC2(7..0):
ADC result of channel 3
After finishing the A to D conversion the processor is informed by
means of an interrupt. The interrupt service routine can now take
the conversion result of channel 3 from CADC2. The result will be
available for about 46µs after the interrupt.
Semiconductor Group
148
User’s Manual July 99