SDA55XX Datasheet, PDF (140/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Default after reset: 00_H
06%
PWC_7 PWC_6 PWC_5
Pulse Width Modulation Unit
3:&/
SFR-Address CC_H
(LSB)
PWC_4 PWC_3 PWC_ 2 PWC_1 PWC_0
%LW   %LW 
This bits are the low order 8 Bits of the 14 Bit PWM-Counter. This
register can only be read.
Default after reset: 00_H
06%
PWM_Tmr
OV
PWC_13
3:&+
PWC_12 PWC_11 PWC_10
SFR-Address CD_H
(LSB)
PWC_ 9 PWC_ 8
3:0B7PU
Start/stop timer when all PWM channels are disabled.
If this bit is set, the PWM timer will be reset and starts counting.
If this bit is cleared, the PWM timer stops.
The PWM_Tmr bit could not be written (set) if one of the PWM
channels is enabled (PWM_en not all zero).
PWM_en register could not be written (set) if the PWM_Tmr bit is
set.
29
%LW   %LW 
Overflow bit for the timer mode.
These bits are the high order 6 Bits of the 14 Bit PWM-Counter.
This register can only be read.
Semiconductor Group
140
User’s Manual July 99