SDA55XX Datasheet, PDF (37/230 Pages) Infineon Technologies AG – Preliminary & Confidential

Preliminary & Confidential
Default after reset: 00_h
(MSB)
PSAVEX
SDA 55xx
Clock System
SFR-Address D7_H
(LSB)
CLK_src PLL_res PLLS
3//6
3//BUVW
&/.BVUF
0: PLL is running
1: PLL is disabled. The system clock is switched to the 6MHz
oscillator clock. The slicer acquisition and the display generator are
switched off.
Note: Bit PLLS can only be set, if bit CLK_src=1.
0: no PLL reset
1: PLL hold in reset
0: System clock (33.3MHz) derived from 200MHz PLL-clock
1: System clock (3MHz) derived from 6MHz oscillator clock
Note: Before the PLL is switched to power save mode (PLLS=1), the SW has to switch
the clock source from 200MHz PLL-clock to the 3MHz oscillator-clock
(CLK_src=1). In this mode the Slicer, Acquisition, DAC and Display Generator are
switched off.
To switch back, the SW has to end the PLL power save mode (PLLS=0), reset the
PLL for 10µs (3 machin cycles, PLL_res=’1’, then ’0’ again), then wait 150µs (38
machine cycles) and switch back to the PLL clock (CLK_src=0).
Semiconductor Group
37
User’s Manual July 99