SDA55XX Datasheet, PDF (137/230 Pages) Infineon Technologies AG – Preliminary & Confidential

Preliminary & Confidential
SDA 55xx
Pulse Width Modulation Unit
If all the channels are disabled then it can be used as a general purpose timer, by
enabling it with PWM_Tmr bit in PWCH.
Setting PWM_Tmr bit switches to timer mode and starts the timer, Timer always starts
from a reset value of 0 (OV also reset to 0). Timer can be stoped any time by turning off
the PWM_Tmr bit.
When timer overflows it sets an over flow bit OV( bit 6) PWCH and interupt bit
CISR0(PWtmr) in the central interrupt register. If the corresponding interrupt enable bit
isEPW(IEN2) is set the interrupt would be serviced. OV bit and PWtmr bits must be reset
by the software.
Note that before utilizing the timer for PWM channels PWM_Tmr bit must be reset.
Note that On reset CISR0(PWtmr) bit is intialized to 0, however if counter overflows this
bit might be set along with OV bit.Howeverclearing OV bit does not clear the
CISR0(PWtmr) bit. Therefore software must clear this bit before enabling the
corresponding interrupt.
14.8
Control registers
All control register for PWM are mapped in the SFR address space. Their address and
bit discription is given below.
Note that controller can write any time into these registers. However registers
PWM_COMP8_X, PWM_CPMP14_X and PWM_CPMPEXT14_X, including the bits
PWM_direct and PWM_PR are double buffered and values from shadow registers are
only loaded into the main register in case timer overflows or timer is stopped (PWME =
00h).of8 bit counter.
Overflow for 8 bit PWM occurs at the overflow of 6 bit counter and overflow for 14 bit
counter occurs at the overflow
When any of the PWM channels is not used associated compare register can be used
as general purpose registers, except PWM_En and PWCOMPEXT14_0 bit 0 and 1..
Semiconductor Group
137
User’s Manual July 99