SDA55XX Datasheet, PDF (155/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Sync System
Character Display Area
Characters and there attributes which are displayed inside this area are free
programmable according to the specifications of the display generator (see also
18.2). The start position of that area can be shifted in horizontal and vertical
direction by programming the horizontal and vertical sync delay registers (SDH
and SDV). The size of that area is defined by the instruction FSR in the display
generator.
Register which allow to set up the screen and sync parameters are given in the
table below.
Table 18 Overview on Sync Register Settings
Parameters
Sync Control Register
VL - Lines / Field
T_h-period - Horizontal Period
F_pixel - Pixel Frequency
T_{vsync_delay} - Sync Delay
T_{hsync_delay} - Sync Delay
BVCR - Beginning
Of Vertical Clamp Phase
EVCR - End
Of Vertical Clamp Phase
T_{h_clmp_b} - Beginning
Of Horizontal Clamp Phase
T_{h_clmp_e} - End
Of Horizontal Clamp Phase
Register
SCR
VLR
HPR
PFR
SDV
SDH
BVCR
EVCR
BHCR
EHCR
Min Value
1 line
15 µs
10 MHz
4 lines
32 pixel
1 line
1 line
0 µs
0 µs
Max Value Step
see below
1024 lines 1 line
122,8 µs 30 ns
32 MHz 73,25
KHz
1024 lines 1 line
2048 pixel 1 pixel
1024 lines 1 line
1024 lines 1 line
122,8 µs 480 ns
122,8 µs 480 ns
Default
625 lines
64 µs
12,01
MHz
32 lines
72 pixel
line 0
line 4
0 µs
4,8 µs
User has to take car for a setting of PFR and SDH so that SDH/PFR is greater
than 2us.
17.1.2 Sync Interrupts
The sync unit delivers interrupts (Horizontal and vertical interrupt) to the
controller to support the recognition of the frequency of an external sync source.
These interrupts are related to the positive edge of the non delayed horizontal
and vertical impulses which can be seen at pins HSYNC and VSYNC.
Semiconductor Group
155
User’s Manual July 99