SDA55XX Datasheet, PDF (85/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Interrupts
7.4
Enabling interrupts
Interrupts are enabled through a set of Interrupt Enable registers (IE0, IE1, IE2 and IE3).
Bits 0 to 5 of the Interrupt Enable registers each individually enable/disable a particular
interrupt source. Overall control is provided by bit 7 of IE0 (EAL). When EAL is set to "0",
all interrupts are disabled: when EAL is set to "1", interrupts are individually enabled or
disabled through the other bits of the Interrupt Enable Registers. EAL may however be
overridden by the DISINT signal which provides a global disable signal for the interrupt
controller.
7.4.1 Interrupt Enable registers (IE0 IE1 IE2 IE3)
The processor has 4 Interrupt Enable registers.The details of the registers are as follows.
For each bit in these registers, a 1 enables the corresponding interrupt and a 0 disables
it.
Default after reset: 00_H
(MSB)
,( ELW DGGUHVVHEOH
EAL
--
EAD
EU
ET1
EX1
SFR Address A8_H
(LSB)
ET0
EX0
EAL
--
EAD
EU
ET1
EX1
ET0
EX0
Enable All Interrupts. When set to "0", all interrupts are disabled.
When set to "1", interrupts are individually enabled/disabled
according to their respective bit selection.
Reserved
Enable or disable Analog to digital convertor Interrupt .
Enable or disable UART nterrupt.
Enable or disable Timer 1 Overflow Interrupt.
Enable or disable External Interrupt 1.
Enable or disable Timer 0 Overflow Interrupt.
Enable or disable External Interrupt 0.
Semiconductor Group
85
User’s Manual July 99