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| SDA55XX Datasheet, PDF (138/230 Pages) Infineon Technologies AG – Preliminary & Confidential | |||
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Preliminary & Confidential
SDA 55xx
Pulse Width Modulation Unit
Default after reset: 00H
(MSB)
PE7
PE6
PE5
3:0B(n
PE4
PE3
SFR-Address &(H
(LSB)
PE2
PE1
PE0
( (
( (
The corresponding PWM-channel is disabled.
P1.i functions as normal bidirectional I/O-port.
The corresponding PWM-channel is enabled. PE0...PE5 are
channels with 8-bit resolution, while PE6 and PE7 are channels
with 14-bit resolution.
Default after reset: 00H
(MSB)
3:0B&203B; WR
SFR-Address C1H-C6H
(LSB)
PC8X_7
PC8X_6
PC8X_5
PC8X_4 PC8X_3 PC8X_2 PC8X_1 PC8X_0
%LW %LW
%LW
%LW
These bits define the high time of the output. If all bits are 0, the high
time is 0 internal clocks. If all bits are 1, the high time of a base cycle
is 63 internal clocks.
If this bit is set, every second PWM-Cycle is stretched by one
internal clock, regardless of the settings of Bit7 ⦠Bit2.
If this bit is set, every fourth PWM-Cycle is stretched by one internal
clock, regardless of the settings of Bit7 ⦠Bit2.
Default after reset: 00H
(MSB)
3:0B&203B;
SFR-Address C7H,C9H
(LSB)
PC14X_7
PC14X_6
PC14X_5
PC14X_4
PC14X_3
PC14X_2
PC14X_1
PC14X_0
%LW %LW
This bits define the high time of the output. If all bits are 0, the high
time is 0 internal clocks. If all bits are 1, the high time of a base cycle
is 255 internal clocks.
Semiconductor Group
138
Userâs Manual July 99
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