SDA55XX Datasheet, PDF (157/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Sync System
Bit
SNC
Function
Sandcastle Sync (Slave mode only)
Two input pins are reserved for synchronisation. These input pins can be
used as two seperated sync inputs or as one single sync input. If two
seperated sync inputs is selected horizontal syncs are fed in at H pin and
vertical syncs are fed in at V pin. If one single input pin is selected H pin
is used as a sandcastle input pin.
0: H/V-sync input at H/V pins
1: Sandcastle input H pin
INT
Interlace / Non-interlace.
TVTpro can either generate an interlaced or a non-interlaced timing.
(Master mode only). Interlaced timing can only be created if VLR is an
odd number.
0: Interlaced timing is generated.
1: Non-interlaced timing is generated.
VP
V-Pin Polarity.
This bit defines the polarity of the V pin (master and slave mode).
0: Normal polarity (active high).
1: Negative polarity.
HP
H-Pin Polarity.
This bit defines the polarity of the H pin. (Master and slave mode).
0: Normal polarity (active high).
1: Negative polarity.
RGB_D(1..0) RGB/COR Delay Circuitry
In some applications of our customers the blanking is fed through other
devices before it is used as a signal to control the multiplexing of
video/RGB-mix. These other devices may create a delay of the blank
signal. If no special effort is taken, this delay would create a vertical band
at the beginning and the end of the active blanking zone.
To compensate this, the generated RGB and the COR signals can be
delayed by TVTpro in reference to the generated blank signal. This delay
is always a multiple of the pixel-frequency from zero delay up to 3 times
pixel delay:
00: zero delay of RGB/COR-output in reference to BLANK-output
01: one pixel delay of RGB/COR-output in reference to BLANK-output
10: two pixel delay of RGB/COR-output in reference to BLANK-output
11: three pixel delay of RGB/COR-output in reference to BLANK-output
Semiconductor Group
157
User’s Manual July 99